In modern communication systems trapezoidal pulse generators are used to shape a signal prior to transmission. A trapezoidal pulse generator converts a digital signal into an analog signal, which is necessary for transmission via a cable or an optical fiber.
FIGS. 1 and 2 illustrate a typical transmitter and a receiver, respectively, of a wireline communication system. The blocks in the transmitter 100 and receiver 200 are connected differentially as indicated by the double lines. Referring now to FIG. 1, a transmitter 100 includes a jitter attenuator 104, a digital encoder 108, a phase locked loop 112, a trapezoidal pulse generator 116 and a line driver 120.
In operation, a clock signal and data are provided to the jitter attenuator 104. The jitter attenuator 104 removes unwanted jitter from the clock signal, and synchronizes the data and the clock signal. The jitter attenuator 104 provides the data to the digital encoder 108. The digital encoder 108 encodes the data according to a standard coding scheme.
The jitter attenuator 104 provides the clock signal to the phase locked loop 112. The phase locked loop 112 multiplies the frequency of the clock signal by an integer number. The clock signal's frequency is multiplied by an integer in order to meet the over-sampling requirement of the trapezoidal pulse generator 116. In this case, the phase locked loop 112 multiplies the clock signal by 4, i.e., increases the clock frequency by 4. The multiplied clock signal is received by the trapezoidal generator 116. The trapezoidal generator 116 also receives the encoded data from the encoder 108.
As mentioned before, the trapezoidal pulse generator 116 converts the digital signal into an analog signal that is suitable for transmission via a cable or optical fiber. Specifically, the trapezoidal pulse generator 116 converts a digital signal, which is a train of square waves, into a trapezoidal shaped signal. The output of the trapezoidal pulse generator 116 is received by a line driver 120. The line driver 120 drives the resistive load of a media 124 such a coaxial cable. In other words, the line driver transmits the analog signal over the coaxial cable 124. In the description that follows, the media 124 will be referred to as the coaxial cable.
Referring now to FIG. 2, a receiver 200 includes a variable gain amplifier (VGA) 204, an equalizer 208, a peak detector (PD) 216, a slicer 240, an analog offset controller (AOC) 212, a clock and data recovery circuit (CDR) 220, an automatic equalizer control (AEC) 224, an analog gain controller (AGC) 228, and a digital decoder 232.
The signal transmitted over a cable 202 is received by the receiver 200. The VGA 204 amplifies the signal to compensate for the frequency-independent loss, also known as resistive loss or flat loss.
The output of the VGA 204 is received by the equalizer 208. The equalizer 208 compensates for the frequency-dependent loss on the cable also known as cable loss. The equalizer 208 boosts the high frequency components of the signal to compensate for the cable loss.
The output of the equalizer 208 is received by the PD 216. In general, the PD 216, which receives an analog output from the equalizer 208, determines the peak of the equalized signal. The output of the equalizer 208 is also received by the AOC 212, which controls through the VGA 204 the differential offset of the receiver. Thus, the AOC 212 forms a feedback loop to adjust through the VGA 204 the differential offset of the receiver, driving the differential offset to 0 V level. The differential offset of the receiver is driven to a 0 V level in order to eliminate harmonic distortion inside the receiver 200.
As discussed before, the output of the equalizer 208 is received by the PD 216. The peak detector determines the peak of the equalized signal (i.e., the output of the equalizer 208) and sends the peak value to the slicer 240. The slicer 240 also receives the output of the equalizer 208. The slicer 240 functions as an analog to digital converter (e.g., a 2 bit A/D converter), which outputs a digital signal using the peak value.
The digital output of the slicer 240 is received by the CDR 220. The CDR 220 extracts the correct clock signal and data from the digital signal and also synchronizes the data and the clock signal. The output of the CDR 220 is received by the decoder 232, which decodes the signal according to a standard decoding scheme.
The analog output of the PD 216 is received by the AGC 228, which controls the gain of the VGA 204. The digital output of the slicer 240 and the output of the CDR 220 are received by the AEC 224, which controls the gain of the equalizer 208 by adjusting the equalizer coefficients or steps.
The trapezoidal pulse generator is now described in detail. FIG. 3 illustrates a conventional trapezoidal pulse generator 300. The trapezoidal pulse generator 300 comprises a current mirror, which is switched in order to charge and discharge an output capacitor. A reference current Iref 304 is mirrored 1:N using a two-stage current mirror formed by transistors 308, 312, 316, 320 and 324. The current through transistors 312 and 316 is Iref, while the current through transistors 320 and 324 is N*Iref. Switches 328 and 332 are operated in a complementary manner to charge and discharge an output capacitor 336, also referred to as Cout.
The waveform generated by the trapezoidal pulse generator 300 is shown in FIG. 4. During a first phase (i.e., t0<t<t1), the switch 328 is closed and the switch 332 is opened. During the first phase, the capacitor 336 is charged by the current N*Iref to a voltage Vout. During a second phase (i.e., t1<t<t2), the switches 328 and 332 are opened. During the second phase, the capacitor 336 holds the voltage Vout. During a third phase (i.e., t2<t<t3), the switch 332 is closed and the switch 328 is opened. During the third phase, the capacitor 336 discharges through the transistor 324. During a fourth phase (i.e., t3<t<t4), the switches 328 and 332 are opened. During the fourth phase, the capacitor 336 holds the voltage Vout. The rate at which the capacitor 336 is charged and discharged determines the slope of the rising edge and falling edge, respectively, of the trapezoidal pulse.
Consider the capacitor 336 being initially not charged. Vout can be represented by the following equations:During the first phase, Vout=(N*Iref)*t/Cout(0<t<t1)  (1)During the second phase, Vout=(N*Iref)*t1/Cout(t1<t<t2)  (2)During the third phase, Vout=(N*Iref)*(t1−t)/Cout(t2<t<t3)  (3)During the fourth phase, Vout=(N*Iref)*(t1−t3)/Cout(t3<t<t4)  (4)
From the foregoing, it is evident that a variation in the capacitance and Iref will cause Vout to vary. The capacitance of a capacitor can vary depending on changes in temperature or process. Also, a variation in the value of a resistor will cause Iref to vary. FIG. 5 illustrates a typical circuit for generating Iref. A resistor Rref is connected in series with a band-gap voltage Vbg and ground. The current Iref through the resistor Rref is equal to Vbg/Rref. While Vbg can be accurately controlled, the resistance value of Rref can vary depending on changes in temperature or process. Thus, a variation in the value of Rref due to differences in process or temperature can cause variation in Iref.
Since Vout varies with the variation in Iref and Vout, the shape of the trapezoidal pulse will vary. The variation in Iref and Cout are not similar. Since Rref and Cout are manufactured from different materials, due to a variation in process or temperature, Rref may increase in value while Cout may decrease in value. Thus, the variation in Iref and Cout causes uncertainty in the trapezoidal pulse shape. The variation in the shape of the trapezoidal pulse may be substantial enough to cause the waveform to fall out of a required template causing error in the data bits.